The present invention generally relates to fabricating nonvolatile semiconductor memory devices. In particular, the present invention relates to improved methods of fabricating SONOS type nonvolatile memory devices.
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), employ a memory cell characterized by a vertical stack of a tunnel oxide, a first polysilicon layer over the tunnel oxide, an ONO (oxide-nitride-oxide) interlevel dielectric over the first polysilicon layer, and a second polysilicon layer over the ONO interlevel dielectric. For example, Guterman et al (IEEE Transactions on Electron Devices, Vol. 26, No. 4, p. 576, 1979) relates to a floating gate nonvolatile memory cell consisting of a floating gate sandwiched between a gate oxide and an interlevel oxide, with a control gate over the interlevel oxide.
Generally speaking, a flash memory cell is programmed by inducing hot electron injection from a portion of the substrate, such as the channel section near the drain region, to the floating gate. Electron injection carries negative charge into the floating gate. The injection mechanism can be induced by grounding the source region and a bulk portion of the substrate and applying a relatively high positive voltage to the control electrode to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain region in order to generate xe2x80x9chotxe2x80x9d (high energy) electrons. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel region through a subsequent xe2x80x9creadxe2x80x9d mode. The magnitude of the read current is used to determine whether or not a flash memory cell is programmed. The act of discharging the floating gate of a flash memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source region of the transistor (source erase or negative gate erase) or between the floating gate and the substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source region and grounding the control gate and the substrate while floating the drain of the respective memory cell.
Subsequently, SONOS (Silicon Oxide Nitride Oxide Silicon) type memory devices have been introduced. See Chan et al, IEEE Electron Device Letters, Vol. 8, No. 3, p. 93, 1987. SONOS type flash memory cells are constructed having a charge trapping non-conducting dielectric layer, typically a silicon nitride layer, sandwiched between two silicon dioxide layers (insulating layers). The nonconducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. Since the electrical charge is trapped locally near whichever side that is used as the drain, this structure can be described as a two-transistor cell, or two-bits per cell. If multi-level is used, then four or more bits per cell can be accomplished. Multi-bit cells enable SONOS type memory devices to have the advantage over others in facilitating the continuing trend increasing the amount of information held/processed on an integrated circuit chip.
SONOS type memory devices offer various advantages. In particular, the erase mechanism of the memory cell is greatly enhanced. Both bits of the memory cell can be erased by applying suitable erase voltages to the gate and the drain for the right bit and to the gate and the source for the left bit. Another advantage includes reduced wearout from cycling thus increasing device longevity. An effect of reading in the reverse direction is that a much higher threshold voltage for the same amount of programming is possible. Thus, to achieve a sufficient delta in the threshold voltage between the programmed and unprogrammed states of the memory cell, a much smaller region of trapped charge is required when the cell is read in the reverse direction than when the cell is read in the forward direction.
The erase mechanism is enhanced when the charge trapping region is made as narrow as possible. Programming in the forward direction and reading in the reverse direction permits limiting the width of the charge trapping region to a narrow region near the drain (right bit) or the source. This allows for much more efficient erasing of the memory cell.
Another advantage of localized charge trapping is that during erase, the region of the nitride away from the drain does not experience deep depletion since the erase occurs near the drain only. The final threshold of the cell after erasing is self limited by the device structure itself. This is in direct contrast to conventional single transistor floating gate flash memory cells which often have deep depletion problems.
Although many advantages are described above, there are at least two disadvantages associated with SONOS type memory devices. One disadvantage is that isolation by LOCOS (LOCal Oxidation of Silicon) takes up a relatively large amount of space. Given the continuing trend towards miniaturization and increased integration of devices on an integrated circuit chip, efficient utilization of space is of increasing importance. Isolation by LOCOS also causes undesirable outgassing of dopants.
Another disadvantage with SONOS type memory devices is that LOCOS formation causes short channeling. There are high temperatures associated with LOCOS formation, often from 800xc2x0 C. to 1,100xc2x0 C. Short channeling is a decrease in the effective channel length, often represented as Leff. Unnecessarily decreasing the effective channel length results in an undesirably large current passing through the transistor at low gate voltages such as when the transistor is in the xe2x80x9coffxe2x80x9d state.
Thermal cycling associated with LOCOS formation also causes an increase in bitline to bitline punch-through leakage. That is, diffusion caused by thermal cycling leads to undesirable leakage between bitlines.
Generally speaking, in the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller features sizes are required. This includes the width and spacing of such features. This trend impacts the design and fabrication of non-volatile semiconductor memory devices, including SONOS type memory devices.
Referring to FIG. 1, a portion of the core region of a prior art SONOS type memory devices according to Mitchell et al U.S. Pat. No. 5,168,334 is shown. FIG. 1 is analogous to FIG. 5 of Mitchell et al U.S. Pat. No. 5,168,334. FIG. 1 shows silicon substrate 25 having field oxide regions 38 and 40, bitlines 44 and 46, ONO trilayer 50/52/54, and polysilicon wordlines 56 and 66. As shown, the structure has unutilized space between wordlines 56 and 66. There is an unmet need in the art to further scale semiconductor memory devices including SONOS type memory devices.
The present invention provides a process for fabricating SONOS type nonvolatile memory devices having increased density. In particular, the present invention provides SONOS type nonvolatile memory devices having an increased density of gates/wordlines in the core region. The number of memory cells within the array can be substantially increased. The xe2x80x9cdouble densedxe2x80x9d SONOS type nonvolatile memory devices typically have a substantially planar structure. The present invention eliminates high temperature thermal cycling associated with LOCOS formation in the core region, thereby minimizing and/or eliminating short channeling. The present invention also eliminates undesirable bird""s beak associated with LOCOS formation which may lead to fewer defects and/or improved scaling.
One aspect of the present invention relates to a method of forming a nonvolatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; forming a conformal insulation material layer around the first set of memory cell gates; and forming a second set of memory cell gates in the core region, wherein each memory cell gate of the second set of memory cell gates is adjacent to at least one memory cell gate of the first set of memory cell gates, each memory cell gate of the first set of memory cell gates is adjacent at least one memory cell gate of the second set of memory cell gates, and the conformal insulation material layer is positioned between each adjacent memory cell gate.
Another aspect of the present invention relates to a method of increasing core gate density in a non-volatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; growing a silicon dioxide layer around the first set of memory cell gates; depositing an insulation material layer conformally over the silicon dioxide layer; depositing a polysilicon layer over the insulation material layer; and planarizing the substrate to form a second set of memory cell gates in the core region, wherein each memory cell gate/wordline of the second set of memory cell gates is adjacent at least one memory cell gate gate/wordline of the first set of memory cell gates, and the silicon dioxide layer and the insulation material layer are positioned between each adjacent memory cell gate.